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? semiconductor components industries, llc, 2012 january, 2012 ? rev. 1 1 publication order number: p3ps850bh/d p3ps850bh timing-safe peak emi reduction ic functional description p3ps850bh is a versatile, timing ? safe peak emi reduction ic. p3ps850bh accepts one input from an external reference, and locks on to it delivering a 1x timing ? safe output clock. p3ps850bh has a frequency selection (fs) control that facilitates selecting one of the two operating frequency ranges. refer to the frequency selection table. the device has an ssextr pin to select different deviations depending upon the value of an external resistor connected at this pin to gnd. p3ps850bh has an mr pin for selecting one of the two modulation rates. pd#/oe provides the power down option. outputs will be tri ? stated when power down is active. p3ps850bh operates over a supply voltage range of 2.3 v to 3.6 v, and is available in an 8 pin wdfn (2 mm x 2 mm) package. general features ? 1x , lvcmos timing ? safe peak emi reduction ? input clock frequency: ? 18 mhz ? 72 mhz ? output clock frequency( timing ? safe): ? 18 mhz ? 72 mhz ? analog frequency deviation selection ? two different modulation rate selection ? power down option for power save ? output buffer strength: 16 ma ? supply voltage: 2.3 v ? 3.6 v ? 8 pin wdfn 2 mm x 2 mm, (tdfn) package ? these devices are pb ? free, halogen free/bfr free and are rohs compliant application ? p3ps850bh is targeted for use in consumer electronic applications like mobile phones, camera modules, mfp and dpf. wdfn8 case 511aq marking diagrams http://onsemi.com pin configuration see detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet. ordering information p3ps850bh 1 dgm 1 dg = specific device code m = date code = pb ? free device 1 2 3 4 8 7 6 5 clkin pd#/oe fs gnd v ssextr mr modout dd
p3ps850bh http://onsemi.com 2 v dd gnd ssextr clkin modout (timing ? safe) pll fs pd#/oe mr figure 1. block diagram table 1. pin description pin# pin name type description 1 clkin i external reference clock input. 2 pd# / oe i power down. pull low to enable power down. outputs will be tri ? stated when power down is en- abled. pull high to disable power down and enable output. no default state. 3 fs i frequency select .no default state. refer to the frequency selection table 4 gnd p ground 5 modout o buffered modulated timing ? safe clock output 6 mr i modulation rate select. when low, selects low modulation rate. selects high modulation rate when pulled high. has an internal pull ? up resistor. 7 ssextr i analog deviation selection through external resistor to gnd. 8 v dd p supply voltage table 2. frequency selection table fs frequency (mhz) 0 18 ? 36 1 36 ? 72 table 3. operating conditions symbol parameter min max unit v dd supply voltage 2.3 3.6 v t a operating temperature ? 20 +85 c c l load capacitance 15 pf c in input capacitance 7 pf
p3ps850bh http://onsemi.com 3 table 4. absolute maximum rating symbol parameter rating unit v dd, v in voltage on any input pin with respect to ground ? 0.5 to +4.6 v t stg storage temperature ? 65 to +125 c t s max. soldering temperature (10 sec) 260 c t j junction temperature 150 c t dv static discharge voltage (as per jedec std22 ? a114 ? b) 2 kv stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. table 5. dc electrical characteristics symbol parameter test conditions min typ max unit v dd supply voltage 2.3 2.7 3.6 v v ih input high voltage 0.65 * v dd v v il input low voltage 0.35 * v dd v i ih input high current v in = v dd 10 a i il input low current v in = 0 v for mr pin 10 a v oh output high voltage i oh = ? 16 ma 0.75 * v dd v v ol output low voltage i ol = 16 ma 0.25 * v dd v i cc static supply current pd#/oe pin pulled to gnd 10 a i dd dynamic supply current unloaded output fs = 0, @ 18 mhz 6 10 ma fs = 0, @ 24 mhz 7 12 fs = 0, @ 36 mhz 10 17 fs = 1, @ 36 mhz 9 14 fs = 1, @ 48 mhz 11 19 fs = 1, @ 72 mhz 16 28 z o output impedance 13 table 6. ac electrical characteristics parameter test conditions min typ max unit input frequency fs = 0 18 24 36 mhz fs = 1 36 48 72 modout fs = 0 18 24 36 fs = 1 36 48 72 duty cycle (note 1 and 2) measured at v dd / 2 45 50 55 % rise time (note 1 and 2) measured between 20% to 80% 0.8 1.2 ns fall time (note 1 and 2 ) measured between 80% to 20% 0.8 1.2 ns 1. all parameters are specified with 15 pf loaded output. 2. parameter is guaranteed by design and characterization. not 100% tested in production.
p3ps850bh http://onsemi.com 4 table 6. ac electrical characteristics parameter unit max typ min test conditions cycle ? to ? cycle jitter (note 2) unloaded output with ssextr pin open fs = 0, 18 mhz 250 350 ps fs = 0, 24 mhz 150 225 fs = 0, 36 mhz 75 125 fs = 1, 36 mhz 150 200 fs = 1, 48 mhz 100 150 fs = 1, 72 mhz 75 125 pll lock time (note 2) stable power supply, valid clock presen- ted on clkin pin, pd# toggled from low to high 1 ms 1. all parameters are specified with 15 pf loaded output. 2. parameter is guaranteed by design and characterization. not 100% tested in production.
p3ps850bh http://onsemi.com 5 deviation versus ssextr resistance charts 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 700 800 900 1000 resistor (k ) deviation ( %) figure 2. deviation vs. ssextr @ 18 mhz (fs = 0) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 700 800 900 1000 resistor (k ) figure 3. deviation vs. ssextr @ 24 mhz (fs = 0) deviation ( %) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 700 800 900 1000 deviation ( %) resistor (k ) figure 4. deviation vs. ssextr @ 27 mhz (fs = 0) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 700 800 900 1000 resistor (k ) figure 5. deviation vs. ssextr @ 30 mhz (fs = 0) deviation ( %) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 700 800 900 1000 deviation ( %) resistor (k ) figure 6. deviation vs. ssextr @ 36 mhz (fs = 0) mr = 0 mr = 1 mr = 0 mr = 1 mr = 0 mr = 1 mr = 0 mr = 1 mr = 0 mr = 1 mr = 0 mr = 1
p3ps850bh http://onsemi.com 6 deviation versus ssextr resistance charts 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 resistor (k ) deviation ( %) figure 7. deviation vs. ssextr @ 36 mhz (fs = 1) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 resistor (k ) figure 8. deviation vs. ssextr @ 48 mhz (fs = 1) deviation ( %) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 deviation ( %) resistor (k ) figure 9. deviation vs. ssextr @ 54 mhz (fs = 1) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 resistor (k ) figure 10. deviation vs. ssextr @ 60 mhz (fs = 1) deviation ( %) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 100 200 300 400 500 600 resistor (k ) figure 11. deviation vs. ssextr @ 72 mhz (fs = 1) deviation ( %) mr = 0 mr = 1 mr = 0 mr = 1 mr = 0 mr = 1 mr = 0 mr = 1 mr = 1 mr = 0
p3ps850bh http://onsemi.com 7 tskew versus ssextr resistance charts 0 5 10 15 20 25 0 100 200 300 400 500 600 700 800 900 1000 1100 resistor (k ) figure 12. tskew vs. ssextr @ 18 mhz (fs = 0) t skew (ns) 0 2 4 6 8 10 12 14 16 18 0 100 200 300 400 500 600 700 800 900 1000 1100 resistor (k ) figure 13. tskew vs. ssextr @ 24 mhz (fs = 0) t skew (ns) 0 2 4 6 8 10 12 14 16 0 100 200 300 400 500 600 700 800 900 1000 1100 t skew (ns) resistor (k ) figure 14. tskew vs. ssextr @ 27 mhz (fs = 0) 0 2 4 6 8 10 12 0 100 200 300 400 500 600 700 800 900 1000 1100 t skew (ns) resistor (k ) figure 15. tskew vs. ssextr @ 36 mhz (fs = 0) 0 2 4 6 8 10 12 0 100 200 300 400 500 600 700 800 900 1000 1100 0 100 200 300 400 500 600 700 800 900 1000 1100 figure 16. tskew vs. ssextr @ 36 mhz (fs = 1) t skew (ns) resistor (k ) 0 1 2 3 4 5 6 7 8 9 10 0 100 200 300 400 500 600 700 800 900 1000 1100 t skew (ns) figure 17. tskew vs. ssextr @ 48 mhz (fs = 1) resistor (k ) mr = 0 mr = 1 mr = 0 mr = 1 mr = 0 mr = 1 mr = 0 mr = 1 mr = 0 mr = 1 mr = 0 mr = 1
p3ps850bh http://onsemi.com 8 tskew versus ssextr resistance charts 0 1 2 3 4 5 6 7 8 0 100 200 300 400 500 600 700 800 900 1000 1100 t skew (ns) figure 18. tskew vs. ssextr @ 54 mhz (fs = 1) resistor (k ) 0 1 2 3 4 5 6 0 100 200 300 400 500 600 700 800 900 1000 1100 figure 19. tskew vs. ssextr @ 72 mhz (fs = 1) resistor (k ) t skew (ns) mr = 0 mr = 1 mr = 0 mr = 1 minimum ssextr resistance versus frequency(for timing ? safe operation) charts 0 10 20 30 40 50 60 70 80 90 100 110 120 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 resistance (k ) figure 20. frequency vs. resistance (fs = 0) frequency (mhz) 0 5 10 15 20 25 30 35 40 45 50 18 20 22 24 26 28 30 32 34 36 figure 21. frequency vs. resistance (fs = 1) frequency (mhz) resistance (k ) mr = 0 mr = 1 mr = 0 mr = 1 note: device ? to ? device variation of deviation and tskew is 10%
p3ps850bh http://onsemi.com 9 switching waveforms t 2 t 1 v dd /2 v dd /2 v dd /2 output figure 22. duty cycle timing t 3 output t 4 20% 80% 20% 80% figure 23. output rise/fall time t skew t skew represents input ? output skew when spread spectrum is on for example, t skew / 2 = 0.20 * t for an input clock of 24 mhz, translates in to (1/24 mhz) * 0.20 = 8.33 ns ???? ???? ???? ???? ???? ???? ??? ??? ??? ? safe output figure 24. input ? output skew input input modout with ssoff timing-safe modout figure 25. typical example of timing ? safe waveform
p3ps850bh http://onsemi.com 10 note: refer pin description table for functionality details. analog deviation control clkin gnd v dd 2.2 fc2 modout modout clock p3ps850bh frequency selection control v dd 0.1 f clkin r rs v dd c1 fs ssextr pd#/oe rx power down control modulation rate control v dd vddin recommended noise reduction filter mr figure 26. typical application schematic 5 7 6 8 4 1 2 3
p3ps850bh http://onsemi.com 11 pcb layout recommendation for optimum device performance, following guidelines are recommended. ? dedicated v dd and gnd planes. ? the device must be isolated from system power supply noise. a 0.1 f and a 2.2 f decoupling capacitor should be mounted on the component side of the board as close to the v dd pin as possible. no vias should be used between the decoupling capacitor and v dd pin. the pcb trace to v dd pin and the ground via should be kept as short as possible. all the v dd pins should have decoupling capacitors. ? in an optimum layout all components are on the same side of the board, minimizing vias through other signal layers. a typical layout is shown in figure 27. as short as possible vdd gnd clkin fs ssextr pd#/oe modout gnd mr as short as possible r rs figure 27. ordering information part number top marking temperature package type shipping ? p3ps850bhg ? 08cr dg ? 20 c to +85 c 8 ? pin (2 mm x 2 mm) wdfn(tdfn) (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *a ?microdot? placed at the end of last row of marking or just below the last row toward the center of package indicates pb ? free.
p3ps850bh http://onsemi.com 12 package dimensions wdfn8 2x2, 0.5p case 511aq issue a notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30mm from terminal. c a seating plane d e 0.10 c a3 a a1 0.10 c dim a min millimeters 0.70 a1 0.00 a3 0.20 ref b 0.20 d 2.00 bsc e 2.00 bsc e 0.50 bsc pin one reference 0.05 c 0.05 c 8x a 0.10 c note 3 l e b b 4 5 8x 1 8 0.05 c 0.50 l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 2.30 0.50 0.78 7x dimensions: millimeters bottom view 0.35 pitch 8x 0.80 0.05 0.30 0.60 max l1 detail a l optional constructions l --- l1 0.15 b top view side view e/2 1 package outline detail b detail a 2x 2x 8x recommended 0.88 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p3ps850bh/d timing ? safe is a trademark of semiconductor components industries, llc (scillc). publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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